Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
u0|irq_mapper |
4 |
30 |
2 |
30 |
32 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_012|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_012 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_011|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_011 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_010 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_009 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_008 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux_001 |
219 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb|adder |
52 |
26 |
0 |
26 |
26 |
26 |
26 |
26 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux|arb |
17 |
0 |
4 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_mux |
1407 |
0 |
0 |
0 |
121 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_012 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_011 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_010 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_009 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_008 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_007 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_006 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_005 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_004 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_003 |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_002 |
112 |
4 |
2 |
4 |
217 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux_001 |
112 |
4 |
2 |
4 |
217 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|rsp_demux |
111 |
1 |
2 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_012 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_011 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_010 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_009 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_008 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_007 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_006 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_005 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_004 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_003 |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_002 |
219 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux_001 |
219 |
0 |
0 |
0 |
110 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_mux |
111 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux_001 |
124 |
4 |
13 |
4 |
217 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|cmd_demux |
135 |
169 |
2 |
169 |
1405 |
169 |
169 |
169 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_instruction_master_limiter |
220 |
0 |
0 |
0 |
230 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_data_master_limiter |
220 |
0 |
0 |
0 |
230 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_014|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_014 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_013|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_013 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_012|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_012 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_011|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_011 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_010|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_010 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_009|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_009 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_008 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_007 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_006 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_005 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_004 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_003 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_002 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001|the_default_decode |
0 |
17 |
0 |
17 |
17 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router_001 |
98 |
0 |
6 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router|the_default_decode |
0 |
17 |
0 |
17 |
17 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|router |
98 |
0 |
6 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|ledr_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|ledr_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|ledr_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_0_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_0_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_0_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex5_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex5_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex5_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex4_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex4_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex4_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex3_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex3_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex3_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex2_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex2_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex2_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex1_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex1_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex1_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex0_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex0_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex0_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|switches_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|switches_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|switches_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_0_s1_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent|uncompressor |
30 |
1 |
0 |
1 |
28 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_agent |
282 |
39 |
50 |
39 |
286 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_instruction_master_agent |
168 |
39 |
77 |
39 |
130 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_data_master_agent |
168 |
39 |
77 |
39 |
130 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|ledr_s1_translator |
97 |
6 |
15 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|timer_0_s1_translator |
81 |
22 |
30 |
22 |
55 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|key_s1_translator |
97 |
6 |
15 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex5_s1_translator |
97 |
6 |
15 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex4_s1_translator |
97 |
6 |
15 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex3_s1_translator |
97 |
6 |
15 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex2_s1_translator |
97 |
6 |
15 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex1_s1_translator |
97 |
6 |
15 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|hex0_s1_translator |
97 |
6 |
15 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|switches_s1_translator |
97 |
6 |
15 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|onchip_memory2_0_s1_translator |
97 |
7 |
4 |
7 |
83 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_translator |
97 |
5 |
5 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|jtag_uart_0_avalon_jtag_slave_translator |
97 |
5 |
16 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_instruction_master_translator |
97 |
52 |
2 |
52 |
91 |
52 |
52 |
52 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0|nios2_gen2_0_data_master_translator |
98 |
12 |
2 |
12 |
91 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
u0|mm_interconnect_0 |
471 |
0 |
0 |
0 |
478 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|timer_0 |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|switches |
12 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2_0|the_altsyncram|auto_generated |
49 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|onchip_memory2_0 |
53 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
u0|nios2_gen2_0|cpu |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|nios2_gen2_0 |
151 |
0 |
0 |
0 |
100 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|ledr |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|key |
8 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0|the_unsaved_jtag_uart_0_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
u0|jtag_uart_0 |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
u0|hex5 |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|hex4 |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|hex3 |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|hex2 |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|hex1 |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0|hex0 |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
u0 |
14 |
0 |
0 |
0 |
56 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |